Fpgatrabajos

Hi Botond We are interested in FPGA development. Our requirement is to take in a video stream in either DVI or HDMI. To decode the video data into RGB values and scale the value of each with an 8 bit value. This brightness value will be supplied on a 3 line interface consisting of clock, data and update. The data is 24 bits shifted in on the rising edge of the clock line, after all 24 bits are clocked in the update will pulse low. After doing the scaling the RGB video data is then recombined with the control bits (delayed if needed to account for scaling time) and then reassembled into either HDMI or DVI. A control pin will configure operation mode, low for HDMI and high for DVI. Xilinx FPGA preferred ideally with internal configuration memory ....the XC3S50AN would...

Reduced computational complexity PTS algorithm, which aims to reduce computational complexity and achieve the same performance for PAPR reduction compared to conventional PTS approaches, is proposed. In the algorithm, a low complexity phase weighting process is implemented, and the key point is the inherent relationship between phase weighting sequences is considered, which results in simplifying the computation for candidate signals The requirement from the project is to create a block simulink depicting the PAPR reduction technique - Transmitter [refer fig 3 of attached paper] and corrosponding receiver for the same. Explanation of each line on Matlab code Refer attached document for further details Project deliverables: 1. Matlab codes and Simulink block 2. Description of ...

Abstract—This paper demonstrates an FPGA implementation of the Reed-Solomon, RS(255,239), codec architecture for the OTN G.709. The RS codec is designed to occupy the least amount of logic blocks, be fast and parameterizable. I am presenting an efficient implementation of the encoder algorithm on reconfigurable devices in addition to a non-finalized version of the decoder. Both encoder and decoder are synthesized to Altera’s StratixII and benchmarks are run against Altera’s Reed Solomon Code. Xelic’s encoder is measured to be about half the size of Altera’s encoder. Effort on optimizing Xelic’s decoder is underway to have an efficient implementation of the decoder algorithm.

I am looking for developers skilled with video transmission as well as using FPGA microcontrollers. This Proof of Concept is to demonstrate control of an AXIS IP camera along with video routing techniques. This project is broken down into tasks: 1. Stream video data from an AXIS IP Camera using its HTTP based API 2. Store video onto a Secure Digital (SD) card on a development board that uses the Xilinx processor 3. Send a video stream to a Remote Video Viewer which is small program written by you (the contractor). 4. Display live video through the HDMI output port that is on the development board The above steps are detailed further in the attached document. At the end of this project the contractor will deliver: 1. Working source code for the ATLYS development board...

The goal of this project is to implement the Rijndael (AES) encryption system using Verilog. To do this, several separate sections of the algorithm will be coded to work together towards the end goal of performing the correct encryption routines. The algorithm lends itself well towards parallel computations acting on separate sections of the data during the different stages in each round. AES encryption is done in rounds, similar to DES and IDEA. Each round of encryption consists of four steps. These steps are byte substitution, row shifting, column transformation, and round key addition. The interaction of these steps can be seen in more detail in the figures below.

I have created the complete working model for thefollowing project..i have spartan 3E and vertex 5 kits available with me ..All that is needed is to optimize the model as it has exceeded the resource requirements of the kits. The complete project will be a camera attached to my computer...the captured image will be sent to fpga board it will perform some image processing like thinning,thresholding,and minuatae point it will send the three minutae points of that image back to computer where they will be saved in a database with a username associated with it..now once i will have my data base ..i need to verify if the required person is in the database or not..i will have to take image again,processing will be done and then the minutae point will be matched with existing in

"Bit level optimization of FIR filters for biomedical application" is the title of my project. noisy lead-I ECG signal in matlab and filter it using LPF. 2. With that specification of fp,fs,alpha-p and alpha-s compute the FIR filters coefficients using FDA tool utility. ...compute the FIR filters coefficients using FDA tool utility. 3. quantize it with Q16.14 format and Q8.7 format. the given problem with the help of ILP applying suitable constraint to reduce the ripples in the stopband but frequency response must be the same with that of no quantization. apply Integer Linear programing on filters coefficient. 5. At last that code should dump in FPGA to verify the result which get the same frequency respone with no quantization but with low space.

I want PS2 Keyboard interface design with Xilinx FPGA VHDL spartan board and a detail report with this project

...someone who can program our new FPGA board with USB3.0. Required skills are: C/C++ and VHDL Good understanding of Eclipse and Visual C++ IDE and ARM GCC Good understanding of Xilinx Spartan 6 FPGAs and Xilinx ISE Good understanding of USB Our board has the following components: 1x USB3.0 Connector 1x CYUSB3014 USB Controller Chip with ARM Processor from Cypress 1X I2C EEPROM for ARM Processor 1x Spartan 6 XC6SLX16 FPGA 1x 1Gbit DDR2 SDRAM connected to the FPGA (Not used currently) 1x 100 MHz Clock for FPGA 2x 100 pin extension connectors Power supplies for USB Chip and FPGA Leds The board features: -Can be used as bus powered or self powered. -Very Small, 45mmx65mm -External connectors have: . More than 100 General purpose I...

Completing this project successfully will guarantee further work for a number of years to come and possibly a paid senior position. We have a very ambitious new embedded machine vision company and we're funded. The first part of this project is explained below. The goal is to design a USB 2.0 circuit which receives real time video...the PC. Plan ahead so that you don't need to redesign the circuit or change too much of the code. Deliverables need to be "arbitratable" on vWorker, so they include: - circuit schematics in gerber format for production of prototype - bill of materials for us to order the hardware components - VHDL program and simple instructions on what software/methods to use to program the FPGA - C# code on the PC side ...

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I need someone to review a circuit design involving an FPGA, PIC microcontroller, a 150MSPS adc/dac by the end of march. The project should only take a day or two.

...block of at least1000 samples is necessary at this high speed. We will not be sampling the continuous stream, just one large block. The processing can be done slower afterwards. Use a Microchip controller if possible as we would like to use other features on such a chip in the design anyway. (And I am familiar with these chips). We are looking for a cheap solution. And to avoid using expensive FPGA/DSP chips. I was thinking something along the lines of a fast ADC and a microchip with parallel port and DMA. If this is not possible however, then its up to you with how best to proceed. The design does not need to be tested. We are just looking for an expert who knows how to proceed with such a problem and can advise and come up with something. We have all the testing ...

IEEE paper implementation of the attached document. XIlinx ISE software VHDL coding of sign language recognition.

Hi, My Name is Avinash Thakare. I'm from hyderabad India. Following are project details: I need the board circuit designer for the FPGA (xilinx Spartan3an). Please let me know if you have previous experience in board circuit design of FPGA based products. Let me know the details then we can move forward. Thanks Avinash My Email: avinashthakare@

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The purpose of this project is to develop a device that can be used in combination with a normal phone to expand its capabilities to use it for VOIP and/or Skype services. The VOIP/S...services. The VOIP/Skype interface should be configurable over the Ethernet interface and can be used from the phone by starting a call using special characters like "**" or "*##". Since the phone now needs to deal with multiple lines, there should also be proper handling to deal with e.g. two incoming calls etc. To make this project I'm using Altera DE2-115 board to implement a voice over IP phone on FPGA using VHDL coding. The final goal is to use SIP and other protocols for VOIP communication such as rtp, g.711, TCP, UDP and Ethernet. And other protocols for the board itsel...

actually am doing my in vlsi (spl).and i need to do the project what i uploaded here in vlsi implementation.i.e first of all i need to write code in matlab and convert it into verilog and dis verilog code need to dump in fpga kit

I need a VHDL code that counts from 0 to 9 and show the output both on character LCD and on LEDs as binary numbers the counter should count every 1 second

Witam zlecę wykonanie projektu generatora obrazów testowych dla monitora na płytkę fpga Spartan, z wykorzystaniem procesora picoBlaze materiały pomocnicze podeślę na maila więcej info na maila scrollock99@

I have a project which is to design an alarmclock cum stop watch by using Xilinx board and VHDL time could be set by a numeric keypad or keyboard and display on the LCD. I have already bought the Xilinx board which the model is Spartan-3A. I am looking for a person who can do it.

Implement an american sign language recognition system using neural networks on the FPGA (xilinx spartan 3E). The signs to be recognized must include the american sign language alphabets A-Z. Assuming a database of hand images of teh alphabets, a neural network engine is to be built and the features extracted from the images should be used in order to recognize the signs. The implementation is to be done on the Xilinx spartan 3E FPGA board with the sign recognized to be displayed on the lcd segment display.

Attached appnote on xilinx on below details. Programming Xilinx CPLDs,FPGAs, and Configuration PROMs on Xilinx In-System Programming Using an Embedded Microcontroller. experience on Firmware implementaion using embedded microcontroller like ( freescale) or any and to program xilinx FPGA . Provide DLL ,an Applications Programming Interface (API),GUI allowing system boards to communicate with applications software running under Microsoft Windows on a host computer. Create using Microsoft C++ in visual studio for DLL and API.

Programming Xilinx CPLDs,FPGAs, and Configuration PROMs on Xilinx In-System Programming Using an Embedded Microcontroller. experience on Firmware implementaion using embedded microcontroller like ( freescale) or any and to program xilinx FPGA . Provide DLL ,an Applications Programming Interface (API),GUI allowing system boards to communicate with applications software running under Microsoft Windows on a host computer. Create using Microsoft C++ in visual studio for DLL and API.

...quality and time respect and also cost, we will continoue to work with him in all our projects. the tasks are very small and easy. We need the following: 1- expert in autocad drawing who can draw 3D design of industrial mechanics and equipments and schematics of PCB boards and cad drawing of products. 2- expert electrical and electronics person who can design circuits, have great experience in FPGA, microcontrollers. Design schematics,routing, read data sheets. 3- signal processing expert. 4- 3D simulation expert who can make design in 3D design 5- mechanical engineer with long experience. 6- MATLAB and simulink expert again, this is task payment based project, and for long relation proof must be provided for experience and bidder must agree on the confidintiality and ...

...and code for programming the Bootloader, Sketch, and GameDuino FPGA. 6) Other activities as needed to provide a complete and maintainable manufacturing package. ## Deliverables Scope of project: 1) Create PCB design combining "Freeduino USB Host" design, the "GameDuino" design, and other small modifications into a single board. Design/size/etc. 2) Create complete bill of materials package, including at least 2 sources for each component. All parts RoHS compliant. 3) Gather all manufacturing notes and document 4) Document all required manufacturing and programming materials (programming adapters, etc.); including but not limited to programming Arduino BootLoader (identical to Freedunio USB Host); programming the Gameduino FPGA; and the Adruino sketch....

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I am in need of a fully working design of an FPGA based oscilloscope, Must be at least 20 Mhz and bidder must provide full analog front end circuit and VHDL code to view the output on a PC via USB or Ethernet. Work must be your own.

We need a pipelined verilog datapath that is formatted to MIPS ISA. We can provide you a non pipelined datapath to use as a reference. We have also included a non-pipelined and pipelined image of what the datapath should look like. It will need ...datapath to use as a reference. We have also included a non-pipelined and pipelined image of what the datapath should look like. It will need to be able to input MIPS assembly code into the program via a .txt file. Additionally, we need this datapath and assembly code to be able to be synthesized on a Spartan 3E FPGA board. Overview: -Design a pipelined version of the datapath - Synthesize the design - Run it on FPGA board using our assembly code - Use the LCD of the FPGA board to display the coordinates of the blo...

Hi, i have the sp601 evaluation board of Xilinx. this board has spartan-6 FPGA and a DDR2 of Elpida. i need someone who could build the FSM that control the MIG of these memory. basic operation - read and write not even with bursts thanks. Zvika.

The main aim is to create a robot which can solve a maze by literally driving through the maze. The bot should be made out of FPGA (if possible spartan 3 starter board) and the bot should be able to remember the path once choosen and should not go back in the same path if it is not bot can use image recognition if needed and the bot has to be autonomous. Needed with in 30 days from now.

Hi, I need a state machine that controls the Wiznet chip W5300 for UDP or Ethernet communication. The scope is to send data on ethernet at (at least) 10 Mbit/s. The state machine should be in Verilog (not VHDL) targeting an FPGA. Further datails in PM.

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PM ME FOR COMPLTETE DETAILS AND ACTUAL ALGORITH...EVERYTHING IS WORKING ON MATLAB The complete project will be a camera attached to my computer...the captured image will be sent to fpga board it will perform some image processing like thinning,thresholding,and minuatae point it will send the three minutae points of that image back to computer where they will be saved in a database with a username associated with it..now once i will have my data base ..i need to verify if the required person is in the database or not..i will have to take image again,processing will be done and then the minutae point will be matched with existing in the database with housdauff distance and person will be indicated .i will be requiring a gui to interact with as well for adding users ,deleting

i have a project that was done on matlab..m files.. i want to get it embeeded on fpga. project is based upon different image processing techniques and then matching with database..

I need to learn Altium designer for PCB making. I want to learn it with the method 'learn by doing'. So here the bid to teach me in a Videoconference all the steps needed to complete a board. Bid for all the lessons you think are necessary and send me PM with detail. I suggest for the 'learning board' a small FPGA board but a very simple one that can be done easily.

idea is to be able to zoom a signal of 50% (algorythm and qualiter is not a mater at that time) entry ntsc composite video 320x240 output ntsc composite 320x240 pixel can be simply squared I'm ok for any suggestion idea of this project is to check ability to handle video with fpga more projects will follow

Hi there, I am looking for a digital designer with experience in VHDL, preferrable on ASIC, but FPGA will be considered as well. I am working on a complex project that will last a long time and I need help with development. Experience with Ethernet, LVDS or DDR would be a plus. I will first start with a small task to ensure that everything goes fine. Once that ends I will provide more and more work. Thank you. Regards, Nick Keywords: VHDL, digital design, electronics, VLSI, ASIC, FPGA

Face Recognition using Eigenfaces in FPGA HDL : Verilog Softwares: Modelsim, ALTERA Quartus II FPGA: ALTERA Cyclone II Need to simulate and synthesize eigenfaces for face-recognition in a FPGA. Eigenfaces for recognition by Matthew Turk and Alex Pentland ( IEEE paper) is the core of this project. Eigenfaces method is the core of this project, which is explained in detail in Eigenfaces for recognition by Matthew Turk and Alex Pentland. This method has been implemented successfully in MATLAB and the code is also freely available, but it has not been implemented in FPGA's extensively due to the memory and processing speed constrains. The Pixel information from greyscale face images (up to 5 images can be used & face images should be from appr...

Face Recognition using Eigenfaces in FPGA HDL : Verilog Softwares: Modelsim, ALTERA Quartus II FPGA: ALTERA Cyclone II Need to simulate and synthesize eigenfaces for face-recognition in a FPGA. Eigenfaces for recognition by Matthew Turk and Alex Pentland ( IEEE paper) is the core of this project. Eigenfaces method is the core of this project, which is explained in detail in Eigenfaces for recognition by Matthew Turk and Alex Pentland. This method has been implemented successfully in MATLAB and the code is also freely available, but it has not been implemented in FPGA's extensively due to the memory and processing speed constrains. The Pixel information from greyscale face images (up to 5 images can be used & face images should be from appr...

I'm working on the VHDL programming for my thesis and one of my task is to write the code for a simple Hello program. The message on the LCD screen should be able to blink on toggling one of the switches. I'm not sure how to make a start on this. Also, there are few things I would like to ask before starting working on it. For further information please contact me on this website. Thanks

He have a need for an experienced PCB designer in the San Francisco Bay area. Candidate will need to come to company site to at times work the engineer. Schematic design was done in Orcad 16.5, and PCB layout to be done in PADS or PCAD. Must be familiar with decoupling high speed components, controlled impedance, differential signals, EMC, FPGA layout, high frequency analog signals and ESD. Individual must be a self-starter, have mechanical chops, a good communicator and creative. Experience with HDMI and DDR2 a huge plus. We need to have one board updated immediately, and if it seems like a fit between you and us, there are several more boards we need to have done. ******NOTE********* If you do not live in the San Francisco Bay are, please do NOT bid. You will be required...

He have a need for an experienced PCB designer in the San Francisco Bay area. Candidate will need to come to company site to at times work the engineer. Schematic design was done in Orcad 16.5, and PCB layout to be done in PADS or PCAD. Must be familiar with decoupling high speed components, controlled impedance, differential signals, EMC, FPGA layout, high frequency analog signals and ESD. Individual must be a self-starter, have mechanical chops, a good communicator and creative. We need to have one board updated immediately, and if it seems like a fit between you and us, there are several more boards we need to have done.

Need to evaluate the FPGA prototyping board Altera cyclone 2 DE1 to design a voice recorder. Design the project using design should be able to record a minimum of 1 minute of audio input and playback clearly through the on-board speaker or an external speaker. In need of the VHDL programme codes and a Report on the analysis and how the design is done.

Xilinx ISE Project – VHDL design for Virtex 6 FPGA The task is to create a Xilinx ISE project to work with the Xilinx ML605 development board and a mating DAC board. The DAC board comes from a company called 4DSP, model FMC204. See Handbook for FMC204 board attached. The ML605 from Xilinx is a development board for the Virtex 6 FPGA. See The FMC204 board plugs into the ML605 via the high density FMC connector. The project is to generate a simple sine wave at 28MHz in the FPGA and have the DAC board produce 4 analogue output signals. The clock on the DAC board is to run at 112Mhz and provide a reference clock to the FPGA. The DAC sample frequency is also 112Msps. There are

The FPGA will replace funcionality presently , implemented via 16 CMOS ICs, gates, monostables, etc. The circuit itself is a frequency multiplier.