MIPS Assembly Pipeline Microprocessor
$250-750 USD
Pagado a la entrega
We need a pipelined verilog datapath that is formatted to MIPS ISA. We can provide you a non pipelined datapath to use as a reference. We have also included a non-pipelined and pipelined image of what the datapath should look like. It will need to be able to input MIPS assembly code into the program via a .txt file.
Additionally, we need this datapath and assembly code to be able to be synthesized on a Spartan 3E FPGA board.
Overview:
-Design a pipelined version of the datapath
- Synthesize the design
- Run it on FPGA board using our assembly code
- Use the LCD of the FPGA board to display the coordinates of the block with the minimum SAD.
Nº del proyecto: #1325578
Sobre el proyecto
10 freelancers están ofertando un promedio de $480 por este trabajo
I have 4 years of experience in verilog and MIPS datapath assembly. The complete synthesizable verilog code is ready. Looking forward to your reply.
Hello! I can deliver the modified processor and the assambly code in 10 working days (2 weeks). I will use a Spartan-3 development board. Deliverables (HDL code, assambly code, other configuration files) will be pro Más
Hello sir ,we can do your project .Send me the full details about your project and we will deliver your project as per your target time.
I am FPGA engineer with over 5 years of experience in designing high-speed digital ICs using Xilinx FPGAs. I designed a few pipelined CPU's. I have access to Spartan 3AN FPGA board (similar to Spartan 3E board).
