Verilog Project for school

The project report must include: 1)Project definition and characterization 2)Concept development and logical design 3)Design entry using Verilog HDL and functional simulation with enough input data and verification 4)Synthesis and implementation with the .ucf file specified 5)Time simulation with enough input data 6)Downloading and Testing Design/Synthesis/Implementation MUST be done using Xilinx ISE Tools and Spartan 3E or Spartan 6(NEXYX 3) Board. I need a freelancer that can do this project and then either walk me through the process or make a video walk through. The attached file contains the project description.