design testbench in SystemVerilog for TCP/UDP/IP packet generation and testing

$250-750 USD

Terminado

Publicado

hace alrededor de 7 años

$250-750 USD

Pagado a la entrega

need to design packet generator according to input parameters (function) and compare checker of received packets according to parameters the generator/tester should be able to generate all UDP/TCP/IP fields including options for TCP/IP code should be readable, modular, well commented and easy to maintain in future target to verify ALTERA FPGA with TSE MAC

FPGA

Verilog / VHDL

ID del proyecto: 13856603

Información sobre el proyecto

5 propuestas

Proyecto remoto

Activo hace 7 años

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@raulbehl

Hello! Please check my profile/reviews to know a bit about me. It would be great if I could help you out. I am currently working as a Verification Engineer with a leading semi-conductor company and my daily job involves working with SV/Verilog. Also, I do have Altera Modelsim installed and running on my PC. So, no installation/setup time would be required. Please do contact to discuss further. Thank you!

$555 USD en 10 días

5,0

(52 comentarios)

5,7

5 freelancers están ofertando un promedio de $462 USD por este trabajo

@shobhitkapoor

HI I have 12+ years of experience with FPGAs and Packet Generators , please let me know further about this project. Thanks SK

$500 USD en 10 días

4,8

(18 comentarios)

4,5

@manojkumardesign

1)Worked on Project module related to RISC Processor 2)Key Assignments include Asynchronous piplined Architecture design, Rank Order filter in VHDL, Modules related to AES Crypto core. I am working in bangalore for 4 years with experience in VHDL & Labview. I am new to this freelancing job but not to this field. If you work with me once, then you will always work with me in future. I can complete your work in stipulated time. Hire me, Lets work together. Looking forward to work with you. Kindly ignore the bidding time left and place the work with trust to get it completed at the earliest. Thank you :)

$300 USD en 7 días