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    System Verilog- NOC design (8 bit split bus) Finalizado left

    CRC module connected on NOC interface. CRC module, CRC interface, NOC interface files will be provided.

    Verilog / VHDL
    $25 (Avg Bid)
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    Write some software Finalizado left

    I need you to develop some software for me. I would like this software to be developed for Windows . Verilog

    Arquitectura de software Windows Desktop
    $22 (Avg Bid)
    $22 Oferta promedio
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    Verliog_6 October Finalizado left

    Task needs to be done in Verilog in 12 hours from now. If you think you can do it, please ping me. I will share details with you.

    Ingeniería eléctrica Electrónica Verilog / VHDL
    $10 - $30
    Sellado
    $10 - $30
    1 ofertas
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    Create Half Adder Module using Verilog Finalizado left

    It is to Create Half Adder Module using Verilog.

    Verilog / VHDL
    $41 (Avg Bid)
    $41 Oferta promedio
    35 ofertas
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    Design Logic Circuits Using Verilog Finalizado left

    It is to Design Logic Circuits Using Verilog.

    Verilog / VHDL
    $30 (Avg Bid)
    $30 Oferta promedio
    7 ofertas
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    verilog code Finalizado left

    FPGA Microcontrolador Arquitectura de software Desarrollo de software Verilog / VHDL
    $414 (Avg Bid)
    $414 Oferta promedio
    31 ofertas
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    verilog design Finalizado left

    verilog design

    FPGA Verilog / VHDL
    $44 (Avg Bid)
    $44 Oferta promedio
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    s/w in verilog Finalizado left

    verilog coding

    PHP Arquitectura de software
    $160 (Avg Bid)
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    3 ofertas
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    Write some Software in verilog - 01/10/2016 06:58 EDT Finalizado left

    verilog code built

    PHP
    $92 (Avg Bid)
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    verilog code built Finalizado left

    FPGA Microcontrolador Arquitectura de software Desarrollo de software Verilog / VHDL
    $311 (Avg Bid)
    $311 Oferta promedio
    21 ofertas
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    urgent requirement of a functional analyst in HDFC bank Finalizado left

    ...banking system) support to users and closure of issues logged by end users. 4. Coordinating with internal teams (IT/Business/Operations) to complete the issue / project related task in a time bound manner. 5. Discussion with Vendor partner to close the requirement understanding and related sign-offs. 6. Data analysis & MIS. Requirement 1: Core Banking Systems Band: E1/E2 No of requirements: 4 Extra requirements: Look for candidates with all of the below keywords "Core Banking", "Finware", "Flexcube" And look for candidates from Banking Domain ONLY with excellent communication skills and good academic qualifications (First Class and above) and candidates with functional knowledge and NOT TECHNICAL. Lo...

    Contabilidad Análisis de negocios Finanzas Intuit QuickBooks Nóminas
    $748 (Avg Bid)
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    5 ofertas
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    Bytewise Checksum in Verilog for 256-bit Avalon Streaming Interface Finalizado left

    This will be a byte-wise streaming accumulated checksum in Verilog for an Avalon streaming interface. Specification document is attached. As indicated with the spec, I am available to answer any questions for clarification or details. I am here to help. Best of luck!

    Verilog / VHDL
    $200 (Avg Bid)
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    3 ofertas
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    verilog question Finalizado left

    i need someone good at verily to help me a couple of tasks.

    Verilog / VHDL
    $155 (Avg Bid)
    $155 Oferta promedio
    1 ofertas
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    Proyecto o concurso privado #11584763 Finalizado left

    Por favor, regístrate o inicia sesión para ver los detalles.

    Arduino Programación en C Programación en C++ Microcontrolador Verilog / VHDL
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    Project for adipdutt Finalizado left

    Hi adipdutt, I noticed your profile and would like to offer you my Verilog design project. We can discuss any details over chat.

    Programación en C
    $250 (Avg Bid)
    $250 Oferta promedio
    1 ofertas
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    Project for ducdctoandh Finalizado left

    Hi ducdctoandh, I noticed your profile and would like to offer you my project (a Verilog set of modules tasks & functions). We can discuss any details over chat

    Programación en C
    $100 (Avg Bid)
    $100 Oferta promedio
    1 ofertas
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    Verilog BCD to decimal decoder Finalizado left

    I need to desing Verilog BCD to decimal decoder Will provide details to bidders. Deadline is 2 days. max price is $30. I will post more work in case of successful completion.

    Ingeniería eléctrica Electrónica Verilog / VHDL
    $22 (Avg Bid)
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    32 ofertas
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    grayscale image processing in Verilog Finalizado left

    lsb based steganography algorithn implenting in fpga with and withou pipelining

    Verilog / VHDL
    $261 (Avg Bid)
    $261 Oferta promedio
    7 ofertas
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    VLSI work. easy Finalizado left

    Hi Plz bid here if you're good in vlsi ...verilog and vhdl... need your help instantly. if you are excellent then apply... Thanks details in PM give me your best hourly rate..for long term

    Diseño digital Ingeniería eléctrica Electrónica Microcontrolador Verilog / VHDL
    $5 / hr (Avg Bid)
    $5 / hr Oferta promedio
    27 ofertas
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    Verilog BCD to decimal decoder Finalizado left

    I need to desing Verilog BCD to decimal decoder Will provide details to bidders. Deadline is 2 days. max price is $30. I will post more work in case of successful completion.

    Ingeniería eléctrica Electrónica Verilog / VHDL
    $22 (Avg Bid)
    $22 Oferta promedio
    25 ofertas
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    VLSI work needed to be done today... Finalizado left

    Its easy task and i want someone to make it done in less than 5 hours. verilog/vhdl...any experience counts... plz apply if you are good and available now... thanks details in chat.... it will be a longterm work...

    Diseño de circuitos Ingeniería eléctrica Electrónica Verilog / VHDL
    $12 / hr (Avg Bid)
    $12 / hr Oferta promedio
    10 ofertas
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    I would like to hire a Verilog / VHDL Designer Finalizado left

    Verilog / VHDL
    $17 (Avg Bid)
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    14 ofertas
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    JD Edwards CNC Consultant Finalizado left

    Looking for a consultant with strong experience in JD Edwards application software through E1 9.x experience and System Administration experience with JD Edwards OneWorld or EnterpriseOne

    Arquitectura de software
    $11 - $18 / hr
    $11 - $18 / hr
    0 ofertas
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    Write some Software -- 2 Finalizado left

    ...Asterisk Client server Explanation of scenario: 1. server A ( asterisk server, with static IP) receiving VoIP calls , with sip protocol, using G711,G729 and/or G723.1 codec and sending calls to Server B 2. Server B ( Asterisk server with PRIVATE NETWORK IP), receiving calls from server A and sending to gateways (GOIP , Addpac , Dinster ,quintum gateway for example) or E1 cards. 3. Number of Server B can be unlimited. 4. Number of Gateways/E1 cards per server B can be unlimited 5. For server B installation need easy to use ISO image that could be booted from USB flash drive, and those USB flash drive will be delivered to our Server B type client (ther termination provider) A. Any mini Linux distribution exam- puppy Linux , linux mint B. Fedora desktop distribution C. Centos...

    Asterisk PBX PHP Arquitectura de software Talento de voz VoIP
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    Write some Software Finalizado left

    ...Client server Explanation of scenario: 1. server A ( asterisk server, with static IP) receiving VoIP calls , with sip protocol, using G711,G729 and/or G723.1 codec and sending calls to Server B 2. Server B ( Asterisk server with PRIVATE NETWORK IP), receiving calls from server A and sending to gateways (GOIP , Addpac , Dinster ,quintum gateway for example) or E1 cards. 3. Number of Server B can be unlimited. 4. Number of Gateways/E1 cards per server B can be unlimited 5. For server B installation need easy to use ISO image that could be booted from USB flash drive, and those USB flash drive will be delivered to our Server B type client (ther termination provider) A. Any mini Linux distribution exam- puppy Linux , linux mint B. Fedora desktop distribution C. Centos 5.8 o...

    Asterisk PBX PHP Arquitectura de software Talento de voz VoIP
    $427 (Avg Bid)
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    Expand the use of E1, 10x times. ¿can it be achieved? Finalizado left

    Expand the use of E1 with 10x times: We know that each E1 (telecom connection) brings 100 DID’s, when we say expand, it means that we want that one E1 have a performance of 10x (it means incoming calls simultaneous at the same second), we know that this is possible but we need to know if there is someone that knows how to expand. Please confirm us, send us an email with your confirmation, then we will continue with the next step, which consists in indicates the picture of the project. We need this for the outgoing calls too. The first phase is using incoming calls. Our contact is: please confirm us if someone can do this expand.

    Asterisk PBX
    $4481 (Avg Bid)
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    electrical project Finalizado left

    i have a project which based upon verilog module based on gates

    Ingeniería eléctrica Electrónica
    $28 (Avg Bid)
    $28 Oferta promedio
    15 ofertas
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    FPGA Design Engineer Finalizado left

    ...efficiency. Develops and applies automation aids, flows and scripts in support of emulation ease-of-use and improvement of equipment utilization. <br /><br />Qualifications<br /><br />Candidate most possess a bachelors or master's degree in electrical engineering or computer science with relevant work or scholastic experience in the following areas: <br /><br />Technical <br />- Experience with Verilog, and/or VHDL coding and simulation <br />- Experience with logic design, synthesis and timing analyses <br />- Experience with FPGA design tools, flows and methodologies <br />- Experience with C/C++ programming language, Python or other scripting language <br />- Familiar with...

    FPGA Java Perl Python Verilog / VHDL
    N/A
    N/A
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    Server Platform Applications Engineer Intern Finalizado left

    Job description<br />A Server Platform Applications Engineer supports enabling the compute s...specifications/documentation to customers describing system feature operation (hardware and software) and direct customer interaction to support problem resolution. <br /><br />Qualifications<br /><br />Electronic or Computer Science Engineering <br />Bachelor's degree Senior year student <br />Master's degree or PhD student preferred <br />Structured programming: C++, Python, Perl, System-C, Verilog <br />Low level software programming: firmware, drivers, assembly; a plus <br />Basic microprocessor architecture (cores, cache, memory controller, interconnect) <br />Compute system ...

    Delphi Java Perl Python
    N/A
    N/A
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    Image steganography implemented on fpga using verilog Finalizado left

    Ingeniería eléctrica Software integrado Ingeniería Gestión de proyectos Verilog / VHDL
    $750 - $1500
    $750 - $1500
    0 ofertas
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    I want built my M.tech VLSI projects Finalizado left

    project name : Implementation of OFDM on FPGA with mixed radix 8-2 algorithm using verilog. I want full blocks and input and output waveform also.

    Formularios electrónicos Electrónica
    $131 (Avg Bid)
    $131 Oferta promedio
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    Implementation of Karatsuba Multiplier in verilog HDL Finalizado left

    Diseño digital Verilog / VHDL
    $159 (Avg Bid)
    $159 Oferta promedio
    3 ofertas
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    I would like to hire a 3D Modeller Finalizado left

    Need to create a rendering of the room and create a drawings of the ductiong cables, stairs etc.. 1 day job, need to work from our university located in E1 London.

    Diseño 3D Renderización 3D
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    system verilog vmm uvm expert Finalizado left

    looking for some help converting vmm env into uvm

    Verilog / VHDL
    $65 (Avg Bid)
    $65 Oferta promedio
    8 ofertas
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    3CX PBX problem Finalizado left

    I needed to reinstall our 3CX PBX software v11 and now we cant setup correctly that. We are using a sangoma netboarder A102 card to connect to E1 however have 2 problems with that. - No outbound audio. We can hear the caller but they dont hear us. - Caller doesnt hear the ringtone when calling to us neither the onhold audio.

    Asterisk PBX Ingeniería de telecomunicaciones
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    Combination creation Finalizado left

    I have eight objects, four of the objects come in two sizes. A, B, C, D, (E1 or E2), (F1 or F2), (G1 or G2), (H1 or H2) E and F cannot be the same size(E1, F1) and (E2, F2) are not a valid combinations. G and H cannot both be size 2 so (G2, F2) is not a valid combination Order is unimportant, give me all valid combinations of 2, 3, 4, 5, 6, and 7 items chosen. Please separate out the 2 item combos into one plain text file. The 3 item combos into another and so on. Please place each combination on it's own line.

    Matemáticas Programación
    $22 (Avg Bid)
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    Image steganography implemented on fpga using verilog Finalizado left

    Data Hiding Using Verilog

    Ingeniería eléctrica Software integrado Ingeniería Gestión de proyectos Verilog / VHDL
    $1159 (Avg Bid)
    $1159 Oferta promedio
    8 ofertas
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    Image steganography implemented on fpga using verilog Finalizado left

    steganography using vhdl on fpga

    Ingeniería eléctrica Software integrado Ingeniería Gestión de proyectos Verilog / VHDL
    $726 (Avg Bid)
    $726 Oferta promedio
    5 ofertas
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    3D Architectural marketing renders Finalizado left

    Hello, I have a project in which I need some 3D interior marketing renders completed. These will be cut-away 3D Views not 2D Views of a 3D model. There are 3 apartment types E, E1 & E2. 1 apartment is single level and 2 apartments are 2 levels. Therefore I will need 5 renders. I have 2D Autocad drawings or if it helps with the cost of the renders can send through 3D Revit models of the apartments. I have attached below images created by a previous rendering company who are currently too busy to carry out this stage of the work. I will need similar quality images. Ideally I would like the work completed within a week of confirming the job. I would like a fixed price however I have just selected the size of project to complete the field. I also would like to ...

    Animación 3D Modelado 3D Renderización 3D 3ds Max SketchUp
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    EtherCAT slave implement in VHDL/Verilog. Finalizado left

    Electrónica Software integrado Verilog / VHDL
    $95 (Avg Bid)
    $95 Oferta promedio
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    I would like to hire a Technical Support Specialist Finalizado left

    Configuration of ISDN E1 lines in Cisco and send calls from SIP server to CISCO ISDN.

    Cisco Soporte técnico
    $169 (Avg Bid)
    Acuerdo de Confidencialidad
    $169 Oferta promedio
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    FPGA-Verilog-Vivado Finalizado left

    produce project in Vivado/verilog for FPGA

    Verilog / VHDL
    $22 / hr (Avg Bid)
    $22 / hr Oferta promedio
    1 ofertas
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    verilog code of data compressor using bit masks Finalizado left

    I have read some papers and understood the basic concepts of a bit-mask data compressor. All I need is a runnable (not necessarily perfect but decently working ) verilog code to realize a data compressor using bit mask.

    Verilog / VHDL
    $112 (Avg Bid)
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    BASIC SQL QUESTIONS Finalizado left

    ...express “all columns”. 6, If a schema satisfies BCNF, then it also satisfies 3NF. 7, A secondary index can be either dense or sparse. 8, Given a hash function h and two search-key values, Ki and kj, if ki≠kj, then h(ki)≠h(kj). 9, ΠLname, Fname, Salary(σsalary>30000(Employee)) is equivalent to σsalary>30000(ΠLname, Fname, Salary(Employee)). 10, since Natural-join operations are associative, (E1 E2) E3 = E1 (E2 E3), the ordering of natural-join is not important for query optimization. Part 2: Case study The following tables form part of a database held in a relational DBMS: Employee(Fname, Minit, Lname, Ssn, Bdate, Address, Sex, Salary, Super_ssn, Dno) Department(Dname, Dnumber, Mgr_ssn, Mgr_start_date) Project(Pname, Pnu...

    Servidor de Microsoft SQL MySQL SQL
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    Elastix to Digium E1 gateway configuration with Singtel ISDN trunk Finalizado left

    Need urgent assistance and help to configure Digium Gateway with Elastix

    Asterisk PBX
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    Single cycle data path MIPS processor in verilog. Finalizado left

    1. Design whole MIPS processor 2. Execute single instruction per cycle 3. I have written the code for the processor but getting few errors in test bench design. 4. I am trying to execute only R and I type instructions (No J type).

    Ingeniería eléctrica Electrónica Ingeniería Verificación de software Verilog / VHDL
    $67 (Avg Bid)
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    4 ofertas
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    Design a16-bit RISC MIPS Processor using verilog and implementing on FPGA board Finalizado left

    Design a16-bit RISC MIPS Processor. Required - Approach, verilog code, test-benches, output wave form, constraints file and implementation on SPARTAN - 6 FPGA board

    Diseño digital FPGA Verilog / VHDL
    $129 (Avg Bid)
    $129 Oferta promedio
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    Project for ahmedmohamed85 Finalizado left

    Hi ahmedmohamed85, I noticed your profile and would like to offer you my project. We can discuss any details over chat. basically just generating verilog code from openCL code via xilinx or altera software.

    Ingeniería eléctrica Electrónica Ingeniería Microcontrolador Verilog / VHDL
    $50 (Avg Bid)
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    1 ofertas
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    FPGA Verilog Design Finalizado left

    The report should include the cover page, the problem statement, explanation of your approach including the reuse of previously developed modules if any, a block diagram, FSM/ASM charts, Verilog codes used, and the waveforms screen-prints for each question. Use a 1Hz clock where needed. State problems encountered at simulation and implementation stages and how they were resolved. Q2: Design a traffic light system where the north-south street has red, amber, green, and turn left green arrow lights and east-west street has only the red, amber and green lights. Amber, Green, and Green Left light should last 1, 3, and 2 time unit respectively. Left turning traffic will be allowed before the straight traffic. In the implementation on FPGA board use LEDs at E13, C14, C4, and A4...

    FPGA Verilog / VHDL
    $53 (Avg Bid)
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    Write some Software Finalizado left

    RSA Encryption Implemented on verilog. Some errors need sorting out.

    Verilog / VHDL
    $29 (Avg Bid)
    $29 Oferta promedio
    4 ofertas
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