Simulating Multiple Gates third installment c + verilog
$60 CAD
Pagado a la entrega
The first installment of the project dealt with the capability to simulate the actions of four very simple gate types, an INV gate, an AND gate, an OR gate and an XOR (exclusive or) gate. The second installment extended that capability by describing the simple logic gates using Verilog, but the Verilog was restricted to descriptions of circuits which only contained a single gate. For the third installment, we will allow our Verilog circuits to contain multiple gates
Nº del proyecto: #22267786
Sobre el proyecto
9 freelancers están ofertando un promedio de $60 por este trabajo
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