Compiler design

$2-8 AUD / hour

Cerrado

Publicado

hace casi 2 años

$2-8 AUD / hour

Looking for a compiler design expert who can do a simple task related to parsing

Verilog / VHDL

Java

C Programming

Software Architecture

C++ Programming

ID del proyecto: 33750076

Información sobre el proyecto

3 propuestas

Proyecto remoto

Activo hace 2 años

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3 freelancers están ofertando un promedio de $7 AUD /hora por este trabajo

@bouchtaben16

Hi, C++ Software engineer here, I have a experience related to compiler design. Contact me for more details Best regards.

$8 AUD en 40 días

5,0

(36 comentarios)

5,8

@EngineerJulius29

HELLO DEAR CLIENT I have gone through your project details and the work is DOABLE since its within my area of EXPERTISE.I will tackle are required guideline to deliver desired goal Please consider my bid. THANKS Am an expert in Electrical, Electronic & Computing Engineering with a demonstrated History of Academia in the Field of Engineering. I have research, Design and Theoretical knowledge in; Electronic Design and prototyping, Embedded (PCB circuit design and Analysis), Network Automation, Wireless Networks ( RAN & RNPO),Optical Networks (Transmission & IP), Deep Learning, RF and Microwave engineering All Programming languages, Object detection and Computer vision, signal processing & Machine learning, Able to Use Design & Simulation Software i.e MATLAB, OPTIWAVE,SYNOPSYS, QUICKFIELD, PROTEUS,AUTOCAD & MAYA.

$5 AUD en 40 días

0,0

(2 comentarios)

0,0

@lgxbslgx

Hi, I am a Committer of the JDK project in the OpenJDK Community and mainly focus on the Javac(Java compiler). I have much experience in compiler area and can help you about parsing or others you mentioned. Best Regards, -- Guoxiong

$8 AUD en 40 días