Sobel and Canny edge detection algorithms on FPGA
₹600-1500 INR
Pagado a la entrega
We need a code in VHDL or Verilog for Sobel and Canny algorithms
Nº del proyecto: #24038705
Sobre el proyecto
5 freelancers están ofertando un promedio de ₹2210 por este trabajo
Hi.. I have gone through your requirements .I have very good experience in VHDL/Verilog.I can do this project perfectly. I'll provide you a high quality work.. looking forward to hearing from you.. THANKS
Hello, I am a FPGA engineer with good experience in Verilog programming. I already have done this type of image processing work on FPGAs. here is some of the top level code. EdgeDetect uEdgeDetect ( .iClk(psync_c Más
I am a RTL design engineer, work on FPGAs on applications of Image/Video/Speech Processing, Network on Chip, Cryptography, Steganography, etc. using Verilog/VHDL, even on System Generator & Chipscope Relevant Skills a Más