Sobel and Canny edge detection algorithms on FPGA

Cerrado Publicado hace 4 años Pagado a la entrega
Cerrado Pagado a la entrega

We need a code in VHDL or Verilog for Sobel and Canny algorithms

FPGA Verilog / VHDL Image Processing

Nº del proyecto: #24038705

Sobre el proyecto

5 propuestas Proyecto remoto Activo hace 3 años

5 freelancers están ofertando un promedio de ₹2210 por este trabajo

Manoj3050

Hello, I am a FPGA engineer with good experience in VHDL and Verilog programming. Actually I have done this type of image processing work on FPGAs. I can work on this very quickly and get this done. Looking forward t Más

₹5000 INR en 7 días
(4 comentarios)
3.3
AbdhullahMR

Hi.. I have gone through your requirements .I have very good experience in VHDL/Verilog.I can do this project perfectly. I'll provide you a high quality work.. looking forward to hearing from you.. THANKS

₹1750 INR en 2 días
(0 comentarios)
0.0
JingyuanJo

Hello, I am a FPGA engineer with good experience in Verilog programming. I already have done this type of image processing work on FPGAs. here is some of the top level code. EdgeDetect uEdgeDetect ( .iClk(psync_c Más

₹1250 INR en 7 días
(0 comentarios)
0.0
SACHINSMUNJI

I am a RTL design engineer, work on FPGAs on applications of Image/Video/Speech Processing, Network on Chip, Cryptography, Steganography, etc. using Verilog/VHDL, even on System Generator & Chipscope Relevant Skills a Más

₹2000 INR en 1 día
(0 comentarios)
0.0