I need to create and minimize 2 small VHDL entities and their corresponding architectures. Can anyone help? I will provide with some files that are the basics to this, but still need to create 2 more.
You need to be expert in VHDL language and have knowledge of computer architecture.
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Dear sir. I have more than 10 years experience in digital design using vhdl please check my profile also please message me so that we can discuss best regards