Design and implementation of SPI interface

Dear sir I have more than 8 years experience in digital design using verilog and vhdl please check my profile also please message me so that we can discuss

I would like to bid this job because I am really suitable for job description: First: I am an Electronics engineer who is very familiar withVHDL/Verilog. In fact, I have done so many project of VHDL/Verilog(Karatsuba multiplier, Nintendo design, encryption algorithm like Sax Hash, Bernstein Hash, HummingBird...Especialy, I participated in a Walker Recognition project(data from Camera to Human Detection(image processing-HOG feature and Adaboost) and display in VGA). Besides,,I implemented the image conpression (wavelet transform). Especially, I have a Zedboard to verify the design and I am very familiar with the SPI protocol. Finally, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers.. Please contact me and let me know if you want any special requirement. Thank you.

Dear Sir, I'm the Verilog/ VHDL expert and the best VHDL freelancer on this site. please contact me and we can discuss more. Thanks. Loi

Hi I have total 10+ years of experinece , I have worked and designed SPI based master slave for commercial IPs as well , I have xilinx based FPGA board to test, I am committed to provide best quality work. I understand master should be implemented in CPLD and SRAM should be have slave , which is used as SPI Slave. Which CPLD you are targetting , please provide little more details ? I am good in understanding of SPI Protocol. Thanks SK

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I am an engineering graduate with experience in electronics and control systems. I seek a long term career within an organization that challenges me intellectually and professionally. I have a propensity to work in challenging environments and am dynamic in nature; something necessary to push new frontiers in delivering the best idea/service/product.

dear sir, we are team of highly experienced professionals. we work in different embedded technology like microcontrollers, fpga, etc. we are interested in this project pls reply.

Dear sir, I believe I am your right candidate to collaborate with you in this project. I'm an senior electronic engineer with more than nine years of experience working with FPGAs, HDLs, Digital Design, DSP, embedded, I have implemented SPI, I2C, RS232 before, I can deliver you a pretty stable model Which SRAM do you have? I look forward to hearing positively from you for further collaboration. Yours Sincerely, Eugenio Salazar

I have been working with verilog more then one year. I have some ended projects on verilog, which work in hardware, not only in simulator. And a have been working with VHDL more then 3 years.

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A proposal has not yet been provided

Am recently working on fpga based vlsi design project as my post graduate project & have enough knowledge on this field.

I have done extensive Verilog Design and SPI can be done very well. I am already familiar and expert with VhDL and Verilog.

Hi, We are experienced engineers with working knowledge in design and implementation SPI protocol, also experts in USB, I2C and several bus protocols. We would like to have a discussion with you to better understand your project and start working on it. -- BR

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I have been designing memories with SPI interfaces the past thee years. My last major project was a DDR2 memory with a SPI interface for configuration and memory access. I just completed 5 testchips with SPI interfaces for control. I use FPGAs to prototype and validate the ASIC designs, so I am familiar with these flows. I would work with you to define the exact requirements. What SRAM would this be talking to, and what interface is needed to the SPI master. If the SRAM is a simple async or synchronous interface, and the only commands needed are read and write, the verilog coding for this should only take one day. Verification and implementation in the CPLD will take a day or two. I quoted 10 days to make sure I have time to get the requirements correct and everything delivered. I quoted the bottom end of your range to get experience completing a project using freelancer. Technically, it should be pretty easy for me to complete, so it is a reasonable amount.

4+ years exp in FPGA/CPLD Design. Xilinx certified Design Engineer. Expertise in FPGA based Power Processor (PPC) and Microblaze. Language expertise in VHDL,Verilog and System Verilog. Process based code structure. Specification,Simulation and functionality documents as part of delivery. Simulation as per spec implementation. Change Request support

I,ve designed and used SPI Interfacing in some project using FPGAs. Also I used Zynq SPI Interface for Write or Read.

I worked on SPI protocol design earlier and having good hands on experience. I will be well suited for this. Looking forward

I already wrote SPI protocol to the FPGA VHDL language and communication between MASTER and SLAVE I am well acquainted with this protocol.