Digital down converter and Digital Up converter

$250-750 USD

Cancelado

Publicado

hace más de 6 años

$250-750 USD

Pagado a la entrega

Digital down converter , Digital Up converter VHDL & Matlab . DDC: 1- Fsample : 16 bit x 400 MSPS Max. 2- Bandwidth : programmable from 100Khz to 20Mhz. 3- IF Tuner : programmable from DC to 100Mhz , resolution 0.5Hz . 4- DDC decimation Range : 8 to 4096 . 5- CFIR : programmable 20 taps( 18 bit coefficient ) . 6- PFIR : programmable 80 tabs ( 18 bit coefficient ). 7- Manual gain control and overflow indicator. DUC: 1- Fsample : 16 bit , 400 MSPS Max . 2- SFDR >115dB. 3- Tuning resolution : 0.0582 Hz. 4- Interpolation range : Programmable 2 to 32768 . 5- CFIR : programmable 20 tabs x 18bit. 6- PFIR : Programmable 80 tab x 18bit . 7- Bypass interpolation filter On/OFF programmable . 8- Gain control up to 60dB . 9- Overflow Indicator .

Digital Design

FPGA

Matlab and Mathematica

Telecommunications Engineering

Verilog / VHDL

ID del proyecto: 14723930

Información sobre el proyecto

9 propuestas

Proyecto remoto

Activo hace 7 años

¿Buscas ganar dinero?

Dirección de email

Beneficios de presentar ofertas en Freelancer

Fija tu plazo y presupuesto

Cobra por tu trabajo

Describe tu propuesta

Es gratis registrarse y presentar ofertas en los trabajos

9 freelancers están ofertando un promedio de $598 USD por este trabajo

@seshupower

Hi, I am a post graduate power electronics engineer and having very good experience in product design and development. I am excellent in embedded design & programming using pic, dspic controllers and MATLAB codding for Power projects, Boot loaders, Bluetooth & GPS designs,CAN communication, EEprom. UART , Protocols for networking, wi-Fi routers,OBD diagnosis with CAN bus protocols

$777 USD en 20 días

4,9

(34 comentarios)

6,2

@luvtomar

I'm a recent Bachelor of Electrical Engineering from Carleton University. I've designed Digital Up & Down Converters in the past with MATLAB and VHDL and am confident I can do it again. Relevant Skills and Experience VHDL, MATLAB, Digital Integrated Electronics Proposed Milestones $277 USD - complete VHDL and MATLAB code

$277 USD en 5 días

4,9

(16 comentarios)

4,5

@Elecguru011

Hi , I am expert FPGA design engineer with major projects done for DSP applications Relevant Skills and Experience VHDL/Verilog , C/C++ , SOC based Design , Altera / Xilinx Proposed Milestones $100 USD - Project Requirements $600 USD - Working Code $21 USD - Testing and Debugging What is your target device Altera or Xilinx

$721 USD en 30 días