A synthesizable implementation of Search engines

Cancelado Publicado Mar 7, 2012 Pagado a la entrega
Cancelado Pagado a la entrega

A synthesizable implementation of Search engines

(Search engines [input is pattern, data in memory, output is match address])

The implementation may be a mixed HW-SW approach.

May include multiple implementations, codes or algorithms.

Use data in block sizes of 512B, 1K, 2K, 4K

Memory input/output in 8, 16, 32 or 64 bits. Engine input/output left up to implementer

Clock of at least 50MHz (if using 90nm library)

The implementation may be a mixed HW-SW approach.

More information will be provided to bidders.

Ingeniería eléctrica Electrónica Ingeniería Mathlab y Mathematica Verilog / VHDL

Nº del proyecto: #1489351

Sobre el proyecto

6 propuestas Proyecto remoto Activo Mar 15, 2012

6 freelancers están ofertando un promedio de $277 por este trabajo

bchandra1955

----Brajesh-----

$333 USD en 21 días
(36 comentarios)
5.3
reallifetech

See details in MB.

$220 USD en 4 días
(19 comentarios)
4.6
aurasky

Hi I have 7 years experience in VLSI domain. I can do this project.

$400 USD en 10 días
(5 comentarios)
4.5
ee4raja

Hi, I have 4+ years of experience in VLSI domain. Looking forward for your favor reply. Thanks

$250 USD en 5 días
(2 comentarios)
3.6
paklancer

Hi, Please see the PMB

$250 USD en 30 días
(0 comentarios)
0.0
nkfree

Nice to meet you, I have good experience in VLSI designs. Please consider me and try me once. Please check PMB. Have a NICE day

$210 USD en 15 días
(0 comentarios)
0.0