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ARM software - SPI to USB mass storage FIFO project.

$500-5000 USD

En curso
Publicado hace más de 12 años

$500-5000 USD

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Embedded USB FIFO Controller This is an embedded firmware project involving an ARM processor. Code will be written in the IAR (prefered) or Code Warrior development environment. A microcontroller will be configured to buffer real-time data stream using a USB flash dongle or HDD. The purpose of the FIFO buffer is to stream audio data from one SPI input to an 8-bit parallel port output. The SPI input device has no handshaking and operates at a constant rate of 250KB/s. The SPI input must be serviced in real time to prevent data loss. The output device uses hardware handshaking and may not be available at all times. The purpose of the FIFO is to minimize loss of SPI data when the FTDI parallel output device is not able to accept data. There will be no processing of the SPI input data stream. It will be output to a parallel port in exactly the same format it was received from the serial port. ## Deliverables Embedded USB FIFO Controller This is an embedded firmware project involving an ARM processor. Code will be written in the IAR or Code Warrior development environment. A microcontroller will be configured to buffer real-time data stream using a USB flash dongle or HDD. The purpose of the FIFO buffer is to stream audio data from one SPI input to an 8-bit parallel port output. The SPI input device has no handshaking and operates at a constant rate of 250KB/s. The SPI input must be serviced in real time to prevent data loss. The output device uses hardware handshaking and may not be available at all times. The purpose of the FIFO is to minimize loss of SPI data when the FTDI parallel output device is not able to accept data. There will be no processing of the SPI input data stream. It will be output to a parallel port in exactly the same format it was received from the serial port. A two-level buffer will be implemented in software. The first level of buffering will use a 1MB SRAM attached to the processor. The purpose of the SRAM is to buffer SPI data during brief periods of time when the parallel output device is not available and during the time that the USB mass storage device is being initialized for writing. Under normal conditions, data will flow from the SPI port into the SRAM FIFO with only a few bytes of buffering necessary. When the FTDI parallel output device attached to the host computer USB port is unavailable to transfer data from the SPI input, the SRAM FIFO will start to fill. When the RAM buffer is more than 50% full, the USB mass storage device will be used to buffer additional data. While the SRAM buffer is less than 50% full, no writing to the USB device will be necessary. This will reduce the possibility of damaging the USB device by exceeding its write endurance. The code developed will include an initialization function, a read thread, and a write thread. The initialization code will set up the microcontroller, configure its clock, memory, input and output pins, and set the SPI mode. In addition, the initialization code must set up the USB controller host mode and detect the presence and size of the attached USB mass storage device. The USB device will be either a large capacity 8GB+ USB FLASH dongle or a DASD USB HDD of ~250GB+. After initialization, two program threads will run concurrently. One thread will record the SPI input stream into the FIFO buffers and manage writing to RAM and USB. This thread must always be ready to accept real-time data via SPI at 250KB/s. A second thread will read from the buffers and output to a parallel output device called the FTDI. The output device uses an 8 bit GPIO port with simple handshaking via a ready bit which must be checked before sending data to the parallel port. Under optimal conditions, the FDTI can empty the FIFO at approximately 10MB/sec. Hardware Implementation The development hardware consists of a Freescale Kinetis K60 embedded processor with a USB interface to a mass storage device. Also included is 1 MByte of external SRAM. The processor receives SPI data on Port 0 from the attached test generator source. The processor can be configured to DMA the SPI data directly to SRAM or internal memory. The processor stores data to the internal USB HDD (or flash dongle) whenever the SRAM buffer is >50% full. There is no need to use a file system on the USB HDD. The programmer may prefer to simply stream data in sequential blocks to eliminate file system code and overhead. The processor outputs data through an 8-bit port by manually checking two control bits. Once valid data is output to the port, the processor must check a ready-to-send pin on the output device. When the output device is ready, the 8 bit data is sent through GPIO pins from the processor to the target FTDI interface. The FTDI interface then retransmits this data via USB to the development host PC. Project Notes ? The code needs to receive a continuous data stream serially at 2 Mbs through the SPI interface while transferring it first to SRAM. The K60 has hardware to transfer data from SPI to SRAM via DMA without processor intervention. ? Under normal conditions, the data in SRAM will now be sent to out the FTDI at a much faster rate than 250KBps, and the SRAM FIFO will not fill, containing only a few bytes. The SRAM FIFO will fill >50% only when the FTDI is disconnected from the host PC and can no longer accept data. This is when the microcontroller starts to store data to the USB mass storage device. ? To test your code, disable the USB port attached to the FTDI on the host system. This will invalidate the "ok to send" bit. The USB dongle should then fill with data at 250KBps. Enabling the USB port on the host PC should then cause the FIFO to empty by flushing data from the USB dongle. Use the VCP driver to direct the data to a file or to Hyperterminal for inspection. ? If the FTDI parallel output device remains unavailable for a long period of time, (when the host PC is totally unresponsive for a Windows update for example), continues to write the data to the USB storage device until it's full and then loops, discarding the oldest data. ? The FIFO board has no user interface, so there are no options to set. Only one file needs to be on the USB mass storage device so no file system may be required (ie. Data can just be written linearly in 512b blocks to the USB dongle), though one may be used if preferred by the programmer. ? Some basic intelligence will be needed to gracefully recover from power failures. If the USB dongle has FIFO data when power is lost, the program should transmit this data when power is restored. The read and write pointers as well as a "USB FIFO has data" flag should be kept in non-volatile FLASH or on the dongle itself and updated at least once each 10 seconds. ? There is 128K of SRAM included on the processor chip itself and 1MB available externally. The microcontroller contains 512KB of FLASH memory for the storage of program code. ? Board schematics are simple. The schematics, microcontroller and FTDI specs can be downloaded here: Download FIFO project schematics Download K60 Microcontroller Datasheet Download FTDI Datasheet We can supply a complete host PC with remote control via logmein, or we can ship the hardware and JTAG programmer to the developer if needed. Code Test Procedure The test generator will create fixed and / or variable patterns. The function of the FIFO will be determined by disconnecting the FTDI from the host PC and then reconnecting it. The data received by the PC will be examined for loss of packets. We hope to lose no more than a few bytes during the disconnect/reconnect process. Power will be removed while the processor is using the USB mass storage device for storage. After power is restored, the test pattern should be transmitted with minimum data loss (1s or so). The test will be repeated with both USB flash drives and a USB HDD.
ID del proyecto: 3532127

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