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    1,644 verilog mux testbench trabajados encontrados, precios en USD

    necesito transmitir datos numericos entre la fpga ne...ingresado en formato decimal en el lcd 7 segmentos, adicional a eso que esta información sea transmitida via puerto uart al computador. los entregarles son el codigo hecho en verilog,( make file, archivos.v ) ademas de brindar una breve explicacion del trabajo realizado. hay un plazo de 15 dias.

    $32 / hr (Avg Bid)
    $32 / hr Oferta Promedio
    6 ofertas

    Necesito para nuestro equipo de 15 ingenieros incorporar dos nuevos ingenieros con ilusión, cierta experiencia y conocimientos en VHDL/Verilog y microprocesadores. Es trabajo a tiempo completo y con estabilidad (2 años). Ubicación: Sevilla y Albacete. Uno en cada sitio.

    $23409 - $58522
    $23409 - $58522
    0 ofertas

    Complete a design that includes most of the elements to be used in the CPU

    $138 (Avg Bid)
    $138 Oferta Promedio
    7 ofertas
    Verilog code 5 días left

    Please do what is in the paper and hand me the code, testing waveforms and synthesized diagrams

    $102 (Avg Bid)
    $102 Oferta Promedio
    5 ofertas

    I need someone to write verilog code and also test .do files for a maze game. The program should output to vga. The rules of the game are simple. You start at a point and have to figure out how to get to the exit just like an actual maze. However, there is a monster chasing you and if he catches you, you are dead. The player's movement should not be

    $174 (Avg Bid)
    $174 Oferta Promedio
    4 ofertas
    8-bit Calculator 2 días left

    A calculator has to bee designed using System Verilog. It includes designing ALU, memory and system controller.

    $145 (Avg Bid)
    $145 Oferta Promedio
    2 ofertas

    I need someone to write verilog code and also test .do files for a simplified board game. The program should output to vga. the game is quite simple ;2 players roll dice and move x amount of squares according to the number rolled. first to the end of the board wins. We can discuss the details. The vga display should be very simple and custom made --

    $155 (Avg Bid)
    $155 Oferta Promedio
    2 ofertas

    Code needs to be ported from Matlab to Verilog

    $119 (Avg Bid)
    $119 Oferta Promedio
    5 ofertas

    The application should use openssl libraries. The user upload a file to encrypt/decrypt. The application can show the performance/metrics of encryption like time and memory. The user can select the different algorithm and mode on the application.

    $619 (Avg Bid)
    $619 Oferta Promedio
    21 ofertas

    Verilog Task with Vivado and Quartus 2. Should be familiar with schematic design in Altera Quartus 2.

    $38 (Avg Bid)
    $38 Oferta Promedio
    5 ofertas

    ...with MAX10 10M50DAF484C7G FPGA * ____________ Final Products: ____________ -A software-level block diagram showing the connections between the System Verilog modules described in pdf -System Verilog implementations of the modules described in pdf. -Valid hardware output. Final Note: Please attach any necessary files with a brief description of the

    $30 (Avg Bid)
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    1 ofertas

    1) Design a Finite State Machine (FSM) using Verilog to control the taillights of a 1965 Ford Thunderbird. 2) Implement your design on FPGA

    $164 (Avg Bid)
    $164 Oferta Promedio
    3 ofertas

    ALU Design as per instructions in Verilog Task . Simulation done using Icarus VERILOG

    $22 (Avg Bid)
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    11 ofertas

    Need someone with expertise in setup live stream server to be used in android. and create a few api. experience with: AWS wowza red5 mux azure nginx antmedia php, mysql

    $222 (Avg Bid)
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    13 ofertas

    I need someone to create video tutorials for VLSI design from basics to advanced concepts. Advanced Digital Design Concepts CMOS Logic fundamentals RTL Design with Verilog HDL's ASIC Design Systhesis Concepts ASIC Design Stratagies Static Timing Analysis Low power design implementation Design and power Constraints Perl/Shell Scripting EDA tools usage

    $480 (Avg Bid)
    $480 Oferta Promedio
    7 ofertas

    Need someone who has the tools and/or ability to convert a relatively simple verilog (.v) file to liberty timing (.lib) format, and who can verify the resulting .lib file. If successful and painless, there will be more such projects.

    $60 (Avg Bid)
    $60 Oferta Promedio
    3 ofertas

    It is required to implement the lyra2z cryptographic algorithm on the FPGA. Series FPGA Ultrascale Kintex language Verilog. [iniciar sesión para ver URL]

    $649 (Avg Bid)
    $649 Oferta Promedio
    9 ofertas

    Hey, I need help with Verilog / Vivado FPGA project. I'll send you details.

    $25 (Avg Bid)
    $25 Oferta Promedio
    14 ofertas

    Hey, I have a project that needs to be done in Verilog and Vivado and I'll share details to anyone interested.

    $25 (Avg Bid)
    $25 Oferta Promedio
    8 ofertas

    Just need to design the Snake Gane as per my specifications. I am using Nexys 4 development board.

    $57 (Avg Bid)
    $57 Oferta Promedio
    6 ofertas
    Project for Loi L. Finalizado left

    ...exactly sure how to fix this (from why I read online maybe I'd need to buffer some of the signals, or maybe implement a FIFO... but I do not quite know tbh). I have a small testbench for my VGA controller but not for the RAM-1P IP (not sure how to implement this one) Project : Take my original, light-weight, code and help me to remove these glitches,

    $50 / hr (Avg Bid)
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    1 ofertas

    Snake Game : 1.) Should run on Altera DE2 Board or on basy3 . 2.) Should Support VGA. 3.)Needed in a 3 days. skills:- verilog software:vivado i need this project in verilog and not in VHDL

    $78 (Avg Bid)
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    5 ofertas

    Task on verilog 3 bit ALU Deadline 1 day Amount USD 40

    $63 (Avg Bid)
    $63 Oferta Promedio
    22 ofertas

    Need a small task on 3 bit ALU using verilog. Deadline 18 hours amount usd 30 .

    $28 (Avg Bid)
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    3 ofertas
    Distance using FPGA Finalizado left

    I work in the Electrical Engineering Field. The project is to create a distance measuring program using verilog. I will be using Basys 3 ( FPGA) and an Ultrasonic sensor ( HC-SR04). The idea is to measure the gap between two vehicles. The sensor will be placed in the front of a toy car and used to measure the gap instantaneously and also save that data

    $117 (Avg Bid)
    $117 Oferta Promedio
    21 ofertas

    I would like to discuss with freelancers having strong expertise in programming languages like VHDL, Verilog, Matlab, embedded C Please reach out to me. Engineering B.Tech. is must

    $16 / hr (Avg Bid)
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    30 ofertas

    I have project ready already just need some help!

    $194 (Avg Bid)
    $194 Oferta Promedio
    9 ofertas

    Hi guys, I've done a simple design to test the SRAM of Digilent Cmod A7 FPGA board. This is how it works: Using a terminal through UART, I send the input data and address to the SRAM. Then I send address where to read, and I get back the data previously written. Everything works OK except the controller. I need someone to review my design and fix it.

    $19 (Avg Bid)
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    6 ofertas

    Any encryption code (AES/RSA) written in VHDL/Verilog in Quartus II for fpga board stratix IV. Please contact for more details.

    $33 (Avg Bid)
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    3 ofertas

    we need a technical content writer who knows the system Verilog, OVM and UVM.

    $143 (Avg Bid)
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    7 ofertas

    This is pavan. I am from the VLSI industry. I need a technical writer to explain 3 subjects(digital electronics, Verilog, and VHDL).

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    17 ofertas

    We are looking for C++ programmer with experience in building GUI using QT. Preferable EDA/ Verilog Experience with background in Electrical Engineering

    $500 (Avg Bid)
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    15 ofertas

    Please refer the att...the attached document. This is the base paper of my project. I want to do my project on 64 bit square root carry select adder. I request you to help me with the coding in Verilog using Xilinx in gate level or switch level modelling. Can you please share the cost and the time line for the code. I will need it as soon as possible.

    $43 (Avg Bid)
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    13 ofertas

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    $174 (Avg Bid)
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    12 ofertas

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    $148 (Avg Bid)
    $148 Oferta Promedio
    4 ofertas

    The aim of the project is to design a BIST controller to insert and detect the faults (defect) like ...Read disturbance, Erase disturbance, Program disturbance, SAF, TF, ADF, CFs, TF, NPSF, Retention fault in FLASH memory by using BIST algorithm like March algorithm using verilog or VHDL in Xilinx or Modelsim. Need Simulation waveforms for the same.

    $410 (Avg Bid)
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    2 ofertas
    DSP48E1 help Finalizado left

    Hi! I need some help with DSP48E1 verilog instantiation.

    $4 / hr (Avg Bid)
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    I want clients Finalizado left

    I need some help with selling my services. I am verilog/ matlab coder and I need customers . you find me a client , I write his/her code and you get paid %30 of the project budget

    $23 (Avg Bid)
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    1 ofertas

    I need to implement the project using fully parallel interleaver and QPP interleaver in FPGA platform. the language used for coding is Verilog and it is synthesized in Xilinx.

    $152 (Avg Bid)
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    I need an Android app. I would like it designed and built. Digital audio worksation function...send feature. effects. delay..reverrb. trac compressor track meters track effect imput track midi imput track record imput. . master buss compressor master buss effect imputss. mux down tob16 bit..24 bit or mp3. share feature.. must have updated function.

    $855 (Avg Bid)
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    16 ofertas

    I need an Android app. I would like it designed and built. Digital audio worksation function...send feature. effects. delay..reverrb. trac compressor track meters track effect imput track midi imput track record imput. . master buss compressor master buss effect imputss. mux down tob16 bit..24 bit or mp3. share feature.. must have updated function.

    $901 (Avg Bid)
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    ...i am looking for Electrical & Electronics engineer Mechanical Engineer Civil Engineer Engineers should be expert in following fields Arduino Matlab Raspberry Pi FPGA Verilog/VHDL Python PCB Design (Eagle/Altium) Solidworks AutoCAD if you are expert in any of above mentioned fields then you can place a bid. We will prefer fresh Freelancers but

    $38 (Avg Bid)
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    110 ofertas
    verilog project Finalizado left

    verilog coding using putty or terminal. if you are interested i will give more information.

    $135 (Avg Bid)
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    27 ofertas
    System verilog Finalizado left

    I want help with system Verilog coding. I have a working code that I want revised a bit.

    $97 (Avg Bid)
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    8 ofertas
    verilog project Finalizado left

    mtech Verilog project

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    looking for someone who can convert Open CL algorithm into FPGA Verilog project

    $180 (Avg Bid)
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    Only experienced developer in FPGA mining and OpenCL GPU mining. I am looking for a freelancer who can convert Open CL algorithm into FPGA Verilog project.

    $2830 (Avg Bid)
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    I am looking for a PHP expert who is experience with using ffmpeg libraries. Requirement is to mux audio and video, create slideshow from images etc which are provided by ffmpeg.

    $213 (Avg Bid)
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    my company is going to build a website for the asic verification. we need a technical content writer who knows the Verilog, system Verilog,uvm and ovm industry subjects.

    $104 (Avg Bid)
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    12 ofertas