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    2,000 e1 verilog trabajados encontrados, precios en USD
    VLSI work. easy Finalizado left

    Hi Plz bid here if you're good in vlsi ...verilog and vhdl... need your help instantly. if you are excellent then apply... Thanks details in PM give me your best hourly rate..for long term

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    I need to desing Verilog BCD to decimal decoder Will provide details to bidders. Deadline is 2 days. max price is $30. I will post more work in case of successful completion.

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    Its easy task and i want someone to make it done in less than 5 hours. verilog/vhdl...any experience counts... plz apply if you are good and available now... thanks details in chat.... it will be a longterm work...

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    Looking for a consultant with strong experience in JD Edwards application software through E1 9.x experience and System Administration experience with JD Edwards OneWorld or EnterpriseOne

    $11 - $18 / hr
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    ...Asterisk Client server Explanation of scenario: 1. server A ( asterisk server, with static IP) receiving VoIP calls , with sip protocol, using G711,G729 and/or G723.1 codec and sending calls to Server B 2. Server B ( Asterisk server with PRIVATE NETWORK IP), receiving calls from server A and sending to gateways (GOIP , Addpac , Dinster ,quintum gateway for example) or E1 cards. 3. Number of Server B can be unlimited. 4. Number of Gateways/E1 cards per server B can be unlimited 5. For server B installation need easy to use ISO image that could be booted from USB flash drive, and those USB flash drive will be delivered to our Server B type client (ther termination provider) A. Any mini Linux distribution exam- puppy Linux , linux mint B. Fedora desktop distribution C. Centos...

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    Write some Software Finalizado left

    ...Client server Explanation of scenario: 1. server A ( asterisk server, with static IP) receiving VoIP calls , with sip protocol, using G711,G729 and/or G723.1 codec and sending calls to Server B 2. Server B ( Asterisk server with PRIVATE NETWORK IP), receiving calls from server A and sending to gateways (GOIP , Addpac , Dinster ,quintum gateway for example) or E1 cards. 3. Number of Server B can be unlimited. 4. Number of Gateways/E1 cards per server B can be unlimited 5. For server B installation need easy to use ISO image that could be booted from USB flash drive, and those USB flash drive will be delivered to our Server B type client (ther termination provider) A. Any mini Linux distribution exam- puppy Linux , linux mint B. Fedora desktop distribution C. Centos 5.8 o...

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    Expand the use of E1 with 10x times: We know that each E1 (telecom connection) brings 100 DID’s, when we say expand, it means that we want that one E1 have a performance of 10x (it means incoming calls simultaneous at the same second), we know that this is possible but we need to know if there is someone that knows how to expand. Please confirm us, send us an email with your confirmation, then we will continue with the next step, which consists in indicates the picture of the project. We need this for the outgoing calls too. The first phase is using incoming calls. Our contact is: please confirm us if someone can do this expand.

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    electrical project Finalizado left

    i have a project which based upon verilog module based on gates

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    FPGA Design Engineer Finalizado left

    ...efficiency. Develops and applies automation aids, flows and scripts in support of emulation ease-of-use and improvement of equipment utilization. <br /><br />Qualifications<br /><br />Candidate most possess a bachelors or master's degree in electrical engineering or computer science with relevant work or scholastic experience in the following areas: <br /><br />Technical <br />- Experience with Verilog, and/or VHDL coding and simulation <br />- Experience with logic design, synthesis and timing analyses <br />- Experience with FPGA design tools, flows and methodologies <br />- Experience with C/C++ programming language, Python or other scripting language <br />- Familiar with...

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    Job description<br />A Server Platform Applications Engineer supports enabling the compute s...specifications/documentation to customers describing system feature operation (hardware and software) and direct customer interaction to support problem resolution. <br /><br />Qualifications<br /><br />Electronic or Computer Science Engineering <br />Bachelor's degree Senior year student <br />Master's degree or PhD student preferred <br />Structured programming: C++, Python, Perl, System-C, Verilog <br />Low level software programming: firmware, drivers, assembly; a plus <br />Basic microprocessor architecture (cores, cache, memory controller, interconnect) <br />Compute system ...

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    project name : Implementation of OFDM on FPGA with mixed radix 8-2 algorithm using verilog. I want full blocks and input and output waveform also.

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    Need to create a rendering of the room and create a drawings of the ductiong cables, stairs etc.. 1 day job, need to work from our university located in E1 London.

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    looking for some help converting vmm env into uvm

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    3CX PBX problem Finalizado left

    I needed to reinstall our 3CX PBX software v11 and now we cant setup correctly that. We are using a sangoma netboarder A102 card to connect to E1 however have 2 problems with that. - No outbound audio. We can hear the caller but they dont hear us. - Caller doesnt hear the ringtone when calling to us neither the onhold audio.

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    Combination creation Finalizado left

    I have eight objects, four of the objects come in two sizes. A, B, C, D, (E1 or E2), (F1 or F2), (G1 or G2), (H1 or H2) E and F cannot be the same size(E1, F1) and (E2, F2) are not a valid combinations. G and H cannot both be size 2 so (G2, F2) is not a valid combination Order is unimportant, give me all valid combinations of 2, 3, 4, 5, 6, and 7 items chosen. Please separate out the 2 item combos into one plain text file. The 3 item combos into another and so on. Please place each combination on it's own line.

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    Hello, I have a project in which I need some 3D interior marketing renders completed. These will be cut-away 3D Views not 2D Views of a 3D model. There are 3 apartment types E, E1 & E2. 1 apartment is single level and 2 apartments are 2 levels. Therefore I will need 5 renders. I have 2D Autocad drawings or if it helps with the cost of the renders can send through 3D Revit models of the apartments. I have attached below images created by a previous rendering company who are currently too busy to carry out this stage of the work. I will need similar quality images. Ideally I would like the work completed within a week of confirming the job. I would like a fixed price however I have just selected the size of project to complete the field. I also would like to ...

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    Configuration of ISDN E1 lines in Cisco and send calls from SIP server to CISCO ISDN.

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    Acuerdo de Confidencialidad
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    FPGA-Verilog-Vivado Finalizado left

    produce project in Vivado/verilog for FPGA

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    I have read some papers and understood the basic concepts of a bit-mask data compressor. All I need is a runnable (not necessarily perfect but decently working ) verilog code to realize a data compressor using bit mask.

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    BASIC SQL QUESTIONS Finalizado left

    ...express “all columns”. 6, If a schema satisfies BCNF, then it also satisfies 3NF. 7, A secondary index can be either dense or sparse. 8, Given a hash function h and two search-key values, Ki and kj, if ki≠kj, then h(ki)≠h(kj). 9, ΠLname, Fname, Salary(σsalary>30000(Employee)) is equivalent to σsalary>30000(ΠLname, Fname, Salary(Employee)). 10, since Natural-join operations are associative, (E1 E2) E3 = E1 (E2 E3), the ordering of natural-join is not important for query optimization. Part 2: Case study The following tables form part of a database held in a relational DBMS: Employee(Fname, Minit, Lname, Ssn, Bdate, Address, Sex, Salary, Super_ssn, Dno) Department(Dname, Dnumber, Mgr_ssn, Mgr_start_date) Project(Pname, Pnu...

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    Need urgent assistance and help to configure Digium Gateway with Elastix

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    1. Design whole MIPS processor 2. Execute single instruction per cycle 3. I have written the code for the processor but getting few errors in test bench design. 4. I am trying to execute only R and I type instructions (No J type).

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    Design a16-bit RISC MIPS Processor. Required - Approach, verilog code, test-benches, output wave form, constraints file and implementation on SPARTAN - 6 FPGA board

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    Hi ahmedmohamed85, I noticed your profile and would like to offer you my project. We can discuss any details over chat. basically just generating verilog code from openCL code via xilinx or altera software.

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    FPGA Verilog Design Finalizado left

    The report should include the cover page, the problem statement, explanation of your approach including the reuse of previously developed modules if any, a block diagram, FSM/ASM charts, Verilog codes used, and the waveforms screen-prints for each question. Use a 1Hz clock where needed. State problems encountered at simulation and implementation stages and how they were resolved. Q2: Design a traffic light system where the north-south street has red, amber, green, and turn left green arrow lights and east-west street has only the red, amber and green lights. Amber, Green, and Green Left light should last 1, 3, and 2 time unit respectively. Left turning traffic will be allowed before the straight traffic. In the implementation on FPGA board use LEDs at E13, C14, C4, and A4...

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    Write some Software Finalizado left

    RSA Encryption Implemented on verilog. Some errors need sorting out.

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    Hi, I need to have telemann concerto twv 51 : e1 from this link all the notes into sibelius please, for all four movements. ,_TWV_51:e1_(Telemann,_Georg_Philipp) The figured bass notation is optional, please make clear whether that is included in your offer. Thanks.

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    Project on VeriLog Finalizado left

    Project detail will be given to those who know VeriLog, So kindly please only bid if you know it and you have worked on it and most important if you can start working right now. No middle man no group man.. only professional who can start working right now.

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    ...Meal. Our customer is various from Hypermarket, Supermarket, Convenience Store, Food Service, Horeca, some of strategic partners are Metro, Aeon, Giant, Lotte, CoopMart CircleK, Family Mart, B'smart, AeonMinimart, Sun Group, Vingroup, Sheraton, Caravelle, Liberty Group Please click the link below for more information: Catalog: We are looking for an experienced copywritter for Website who is able to write content, design image and also has sense of making the content attractive for reader, not just only a boring article like old newspaper We will provide you all necessary information including story for each tab, high quality image. However, some content we don't have image, therefore

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    Destacado Urgente
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    Project for bsse2059 Finalizado left

    ...you estimate to work on this and we can arrange our budget accordingly. We are also looking for a frequent programmer, and this can be the first of many projects we can work together. Best Regards, Leonardo Baggio Sao Paulo, Brazil --- Project brief: We need a simple iOS app that will do the following: 1) CRUD (Create, Read, Update e Delete) through our existing API for the following Entities: E1 - Meetings (meet_id : int, date : datetime, locale : string, company_id : int, meeting_type : MeetingType(), createdby_user: User()) E2 - Meeting Agenda Item (agenda_id : int, meet_id : int, title : string, user_in_charge: User(), duration_minutes: int, order:int, createdby_user: User()) E3 - AgendaItem_Comments (agenda_id : int, agendacomment_id:int, insertion_date: datetime, tex...

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    design 32 bit divider

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    Dear Sir/Madam, Thank you for your attention on this task. The motherboard with embedded cpu ECS Elitegroup ECS AMD E1-2100 Dual Core Processor Mini ITX DDR3 1333 Motherboard KBN-I/2100 (1.1) is currently selling on for $43 dollars. I am looking for wholesale price. Could you please find a supplier that can offer wholesale price for me? Before I reward this task to you, please send me the following information for the supplier: 1. company address, 2. contact person, 3. max quantity that can supply per month (I can import 50+ / month), 4. and price / unit. Before I reward this task to you, I don't need email address and contact phone number for the supplier. This is trying to fair to you, because I haven't

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    *overview Display a menu for the user to select from the following options, once the Courses arraylist is fully populated: 0. Input File, Print Contents 1. Sort & Print by Course Name 2. Sort & Print by Course Title 3. Search by Course Name 4. Search by Course Title 5. Add Course to Catalog File 6. Quit Full instructions inside file: Project , please follow all instructions and you must use code from the powerpoint. *must complete it within 2 days

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    Dear Sir/Madam, Thank you for your attention on this task. The motherboard with embedded cpu ECS Elitegroup ECS AMD E1-2100 Dual Core Processor Mini ITX DDR3 1333 Motherboard KBN-I/2100 (1.1) is currently selling on for $43 dollars. I am looking for wholesale price. Could you please find a supplier that can offer wholesale price for me? Before I reward this task to you, please send me the following information for the supplier: 1. company address, 2. contact person, 3. max quantity that can supply per month (I can import 50+ / month), 4. and price / unit. Before I reward this task to you, I don't need email address and contact phone number for the supplier. This is trying to fair to you, because I haven't rewarded

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    Hello, Im use Joomla and Virtuemart 3. I have add a button to share my product detail page on Facebook, but it do not working. My url : See attached my code.

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    Hello, Im use Joomla and Virtuemart 3. I have add a button to share my product detail page on Facebook, but it do not working. My url : See attached my code.

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    I need a solution to to create new site collections based on a template that i can define myself on Office365 (SharePoint Online). What it should do: - On the ROOT site collection / site I click on a button. This shows me a list ...(site_name) with the metadata (sitetitle, owner name, shared or not, department name --> this is used for search later on). Also the default document library should have a default value on the document content type; named department (this will be the department name that is entered in step 1). - Permissions: the owner name will get the full permissions on the site collection / site. I have a Office 365 E1 license. This is project 1 of a lot more. Like to get offers only of people who read this requirements very good and know what they are t...

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    A verilog code for 32bit single precision floating point addition unit. The detail will be provided.

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    It is to make Hardware Design with Verilog.

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    ...native Verilog (or VHDL) source capable of being synthesized that has been tested, and is functional. Further details are: 1. Will measure a frequency input, with a 1Hz resolution from 0 to 65.535kHz (65535Hz) maximum. The resolution should be typically 100millihertz for a stable 1Hz reading. 2. The output will be a 16bit word representing the frequency in Hertz (Hz). 3. Reset is active high. When reset is high, the output is set to 0. 4. Conversion output will be real time (so a period measuring technique could be required). 5. Data valid goes true (high when active data is stable). 6. A 300MHz clock is available however may be changed to 400 or 500 if needed. An additional 25MHz clock is available if required. 7. The target FPGA will be a Xilinx Spartan 6 XC6LX9. ...

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    abel coding Finalizado left

    convert abel to verilog

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    verilog coding Finalizado left

    prepare some verilog code

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    Hi Ars4r3Lancing, I noticed your profile and would like to offer you my project. We can discuss any details over chat. I have some simple XILINX cpld file written in .abl I want to be converted to verilog, to run on XC2C64A cpld. These are quite basic, and I have a number of them. Are u interested in this task ?

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    Project for RiverK330 Finalizado left

    Hi RiverK330, I noticed your profile and would like to offer you my project. We can discuss any details over chat. I have a number of XILINX CLPD .abl files I want rewritten in verilog. Are you interested ? They are quite simple...64 macrocell cpld devices. Are you familiar w .abl ?

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